We cordially invite you to attend this webinar on Mixed Signal Visualization and Debugging. This is an introduction of the capabilities of StarVision Pro and how it can be used to assist engineers on visualizing and debugging various forms of netlists.
What you will learn:
Visualize: Render schematics on the fly for VHDL/Verilog/Spice level netlists to understand function of design easily. Supported formats include Verilog, VHDL, SystemVerilog, Liberty, SPICE, HSPICE, Spectre, Calibre, CDL, DSPF, SPEF.
Prune: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists with the ‘cone view’, for reuse as IP or external use in partial simulation
Clock Domain Analyzer: Visualize and detect different clock domains in the design. Configure Clock cells and also verify the clock domain crossing.
Cross-Probe: Drag & drop selected components/nets between all design views (schematic, logic cone, Parasitic window and source code view and simulation data) to cross probe and shorten debug time, especially during tape-out for full chip debug. Also ability to cross-probe analog and digital simulation data on the netlist
Parasitic: Visualize and analyze parasitic networks (Post layout formats: DSPF, RSPF, SPEF) and create SPICE netlists for critical path simulation
Netlist Reduction: Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function
Skill Export: Export schematics and schematic fragments into Cadence Virtuoso. Schematic for further optimization and debugging using in-build SKILL exporter and Symbol utility package.
ERC Check: Verify/debug connectivity especially for multi fan-in and fan-out nets by identifying floating input and output nets, heavy connected nets, etc.
Hierarchy vs Flat: Ability to convert a Flat netlist into hierarchy and a hierarchical netlist into Flat using our extensive API tcl support
Search & Cone: Using "Search and Cone" Feature to find that one transistor/component/module/net/port/gate in large flattened Netlist.
SOC or Mixed Signal Design: Visualize, Debug and Analyze the RTL, GATE and SPICE Design in one cockpit!
Document: Generate design statistics & reports: Instance & primitive counts
TCL API: Extend functionality of StarVision to match project needs by interfacing with the open database through tcl scripts and in batch mode
Identifying Differences in Schematics: Extend the capabilities of the tool to identify differences between designs.